Industry’s first 40-nm FPGAs and HardCopy ASICs

May 23rd, 2008 • Related • Filed Under

Enabling designers to achieve new levels of integration and innovation, Altera Corporation announced the industry’s first 40-nm FPGAs and HardCopy® ASICs. The Stratix® IV FPGAs and HardCopy IV ASICs, both with transceivers options, provide unprecedented densities, performance and low-power leadership. For the first time, Altera offers a transceiver-based ASIC option with the new HardCopy IV ASIC family. Using the Stratix FPGAs in design delivers the benefits of FPGA hardware and software co-design and co-verification—saving months in time to market—and the use of HardCopy ASICs delivers the benefits of ASICs in production. Today’s announcement significantly widens the density, performance and low-power advantages of the Stratix series versus competing offerings. Combined with the HardCopy ASIC family, Altera is the only company that can offer a complete high-performance solution that allows designers to quickly move from concept to volume production.

Stratix® IV GX FPGAs and HardCopy® IV GX ASICs with embedded transceivers deliver breakthrough levels of system bandwidth and power efficiency for high-end applications, allowing you to innovate without compromise. The transceivers are based on 40-nm technology and include a number of features that ensure excellent jitter performance combined with superior signal integrity for both backplane and chip-to-chip applications. Building on the success of Stratix II GX transceivers, Stratix IV GX FPGA and HardCopy IV GX ASIC transceivers support emerging standards and proprietary serial protocols. The transceivers include several digital blocks that you can configure to simplify the implementation of these protocols.

The Stratix IV family has up to 680K logic elements (LEs), 2X bigger than Altera’s Stratix III family, currently the largest FPGAs on the market. The HardCopy IV ASIC family offers equivalent densities as the Stratix IV devices and features up to 13.3 million gates. Altera® 40-nm devices meet the diverse high-end application needs in a large number of markets such as wireless and wireline communications, military, broadcast and ASIC prototyping. Stratix IV FPGAs offer vertical migration within each family variant providing the most flexibility in device selection. In addition, a vertical migration path exists between Stratix III and Stratix IV E devices, so you can start designing on a Stratix III device today and move to a higher density Stratix IV E device without changing your PCB.

With the increasing demand for services such as video over Internet, high-speed wireless data and digital TV, designers need to deliver solutions that provide higher data rates, higher interface bandwidths, and increased data processing all in a power-efficient manner. To address these design challenges, Altera is leveraging its innovations in transceivers, memory interfaces, low-power technology and FPGA core architecture to offer new capabilities with its 40-nm devices. To address the low-power demands of customers, the Stratix IV family members feature Altera’s patented Programmable Power Technology. This power-saving technology optimizes logic, DSP and memory blocks to maximize performance where needed while delivering the lowest power elsewhere in the design.

Without compromising the performance required for compute-intensive applications, Stratix IV DSP blocks provide the lowest power, lowest cost, and smallest footprint programmable processing solution available. Both Stratix IV GX and Stratix IV E family variants provide a DSP- and memory-rich, highly parallel alternative to digital signal processors. The combination of Stratix IV FPGAs and HardCopy IV ASICs enables highly integrated SoC solutions meeting stringent power budgets and significantly lowering total cost of ownership for wireless basestation OEMs. Stratix IV FPGAs will be a key piece in next-generation 40-Gbps and 100-Gbps architectures by enabling high-speed packet processing, traffic management, security, and encapsulation solutions. Altera’s Stratix IV GX FPGAs meet these requirements with fast DSP, reliable throughput to multi-gigabit open systems data buses, and easy-to-document work flow. Stratix IV FPGAs are the world’s biggest and fastest FPGAs, making them the ideal choice for use in ASIC prototyping platforms when you are performing verification of your next ASIC or ASSP design.

Manufactured on TSMC’s 40-nm process, the Stratix IV FPGA family is comprised of two variants, an enhanced variant rich with memory and digital signal processing (DSP) resources (Stratix IV E FPGAs) and an enhanced variant with transceivers (Stratix IV GX FPGAs). Stratix IV GX FPGAs offer up to 48 transceivers operating at up to 8.5 Gbps, which provides designers with the industry’s highest available bandwidth, more than twice the bandwidth of any other FPGA. Stratix IV GX FPGAs also feature hard intellectual property (IP) support for PCI Express (PCIe) Gen 1 and 2 and also supports a wide range of protocols including, Serial RapidIO®, XAUI (including DDR XAUI), CPRI (including 6G CPRI), CEI 6G, Interlaken and Ethernet.

Altera’s 40-nm solutions enable new levels of system-on-a-chip (SoC) integration and allow you to innovate products without compromise. Stratix® IV FPGAs offer unprecedented system bandwidth with 8.5 Gbps transceivers and fast DDR3 memory interfaces on a fabric that delivers the highest density, the highest performance, and the lowest power. Stratix IV FPGAs, when coupled with HardCopy® IV ASICs, provide the benefits of FPGAs and ASICs using low-risk prototyping.

Combined with Quartus® II productivity tools and technology solutions, Altera’s 40-nm portfolio meets the requirements of high-end digital systems in many end markets such as wireless, wireline, military, and broadcast, and application areas such as digital signal processing (DSP), embedded processing, memory interfaces, and ASIC prototyping.

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